Fundamentals of Digital Logic with Vhdl Design. (Record no. 2945)
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| control field | EBC6843013 |
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| control field | MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20260528153354.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
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| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 260525s2022 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781264364282 |
| Qualifying information | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9781260597783 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (MiAaPQ)EBC6843013 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (Au-PeEL)EBL6843013 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)1292360823 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | MiAaPQ |
| Language of cataloging | eng |
| Description conventions | rda |
| -- | pn |
| Transcribing agency | MiAaPQ |
| Modifying agency | MiAaPQ |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | CD973.D53 .B769 2023 |
| 082 0# - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 025.34140285 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Brown, Stephen. |
| 245 10 - TITLE STATEMENT | |
| Title | Fundamentals of Digital Logic with Vhdl Design. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 4th ed. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | New York : |
| Name of producer, publisher, distributor, manufacturer | McGraw-Hill US Higher Ed ISE, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2022. |
| 264 #4 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Date of production, publication, distribution, manufacture, or copyright notice | �2023. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (839 pages) |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Cover -- Title Page -- Copyright -- Dedication -- About the Authors -- Preface -- Acknowledgments -- Contents -- Chapter 1: Introduction -- 1.1 Digital Hardware -- 1.1.1 Standard Chips -- 1.1.2 Programmable Logic Devices -- 1.1.3 Custom-Designed Chips -- 1.2 The Design Process -- 1.3 Structure of a Computer -- 1.4 Logic Circuit Design in This Book -- 1.5 Digital Representation of Information -- 1.5.1 Binary Numbers -- 1.5.2 Conversion between Decimal and Binary Systems -- 1.5.3 ASCII Character Code -- 1.5.4 Digital and Analog Information -- 1.6 Theory and Practice -- Problems -- Chapter 2: Introduction to Logic Circuits -- 2.1 Variables and Functions -- 2.2 Inversion -- 2.3 Truth Tables -- 2.4 Logic Gates and Networks -- 2.4.1 Analysis of a Logic Network -- 2.5 Boolean Algebra -- 2.5.1 The Venn Diagram -- 2.5.2 Notation and Terminology -- 2.5.3 Precedence of Operations -- 2.6 Synthesis Using AND, OR, and NOT Gates -- 2.6.1 Sum-of-Products and Product-of-Sums Forms -- 2.7 NAND and NOR Logic Networks -- 2.8 Design Examples -- 2.8.1 Three-Way Light Control -- 2.8.2 Multiplexer Circuit -- 2.8.3 Number Display -- 2.9 Introduction to CAD Tools -- 2.9.1 Design Entry -- 2.9.2 Logic Synthesis -- 2.9.3 Functional Simulation -- 2.9.4 Physical Design -- 2.9.5 Timing Analysis -- 2.9.6 Circuit Implementation -- 2.9.7 Complete Design Flow -- 2.10 Introduction to VHDL -- 2.10.1 Structural Specification of Logic Circuits -- 2.10.2 Behavioral Specification of Logic Circuits -- 2.10.3 Hierarchical VHDL Code -- 2.10.4 How not to Write VHDL Code -- 2.11 Minimization and Karnaugh Maps -- 2.12 Strategy for Minimization -- 2.12.1 Terminology -- 2.12.2 Minimization Procedure -- 2.13 Minimization of Product-of-Sums Forms -- 2.14 Incompletely Specified Functions -- 2.15 Multiple-Output Circuits -- 2.16 Concluding Remarks -- 2.17 Examples of Solved Problems -- Problems. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | References -- Chapter 3: Number Representation and Arithmetic Circuits -- 3.1 Positional Number Representation -- 3.1.1 Unsigned Integers -- 3.1.2 Octal and Hexadecimal Representations -- 3.2 Addition of Unsigned Numbers -- 3.2.1 Decomposed Full-Adder -- 3.2.2 Ripple-Carry Adder -- 3.2.3 Design Example -- 3.3 Signed Numbers -- 3.3.1 Negative Numbers -- 3.3.2 Addition and Subtraction -- 3.3.3 Adder and Subtractor Unit -- 3.3.4 Radix-Complement Schemes. -- 3.3.5 Arithmetic Overflow -- 3.3.6 Performance Issues -- 3.4 Fast Adders -- 3.4.1 Carry-Lookahead Adder -- 3.5 Design of Arithmetic Circuits Using CAD Tools -- 3.5.1 Design of Arithmetic Circuits Using Schematic Capture -- 3.5.2 Design of Arithmetic Circuits Using VHDL -- 3.5.3 Representation of Numbers in VHDL Code -- 3.5.4 Arithmetic Assignment Statements -- 3.6 Multiplication -- 3.6.1 Array Multiplier for Unsigned Numbers -- 3.6.2 Multiplication of Signed Numbers -- 3.7 Other Number Representations -- 3.7.1 Fixed-Point Numbers -- 3.7.2 Floating-Point Numbers -- 3.7.3 Binary-Coded-Decimal Representation -- 3.8 Examples of Solved Problems -- Problems -- Reference -- Chapter 4: Combinational-Circuit Building Blocks -- 4.1 Multiplexers -- 4.1.1 Synthesis of Logic Functions Using Multiplexers -- 4.1.2 Multiplexer Synthesis Using Shannon's Expansion -- 4.2 Decoders -- 4.2.1 Demultiplexers -- 4.3 Encoders -- 4.3.1 Binary Encoders -- 4.3.2 Priority Encoders -- 4.4 Code Converters -- 4.5 Arithmetic Comparison Circuits -- 4.6 VHDL for Combinational Circuits -- 4.6.1 Assignment Statements -- 4.6.2 Selected Signal Assignment -- 4.6.3 Conditional Signal Assignment -- 4.6.4 Generate Statements -- 4.6.5 Concurrent and Sequential Assignment Statements -- 4.6.6 Process Statement -- 4.6.7 Case Statement -- 4.6.8 VHDL Operators -- 4.7 Concluding Remarks -- 4.8 Examples of Solved Problems -- Problems. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Chapter 5: Flip-Flops, Registers, and Counters -- 5.1 Basic Latch -- 5.2 Gated SR Latch -- 5.2.1 Gated SR Latch with NAND Gates -- 5.3 Gated D Latch -- 5.3.1 Effects of Propagation Delays -- 5.4 Edge-Triggered D Flip-Flops -- 5.4.1 M-S D Flip-Flop -- 5.4.2 Other Types of Edge-Triggered D Flip-Flops -- 5.4.3 D Flip-Flops with Clear and Preset -- 5.4.4 Flip-Flop Timing Parameters -- 5.5 T Flip-Flop -- 5.6 JK Flip-Flop -- 5.7 Summary of Terminology -- 5.8 Registers -- 5.8.1 Shift Register -- 5.8.2 Parallel-Access Shift Register -- 5.9 Counters -- 5.9.1 Asynchronous Counters -- 5.9.2 Synchronous Counters -- 5.9.3 Counters with Parallel Load -- 5.10 Reset Synchronization -- 5.11 Other Types of Counters -- 5.11.1 BCD Counter -- 5.11.2 Ring Counter -- 5.11.3 Johnson Counter -- 5.11.4 Remarks on Counter Design -- 5.12 Using Storage Elements with CAD Tools -- 5.12.1 Including Storage Elements in Schematics -- 5.12.2 Using VHDL Constructs for Storage Elements -- 5.13 Using VHDL Sequential Statements for Registers and Counters -- 5.13.1 Flip-Flops and Registers with Enable Inputs -- 5.13.2 Shift Registers with Enable Inputs -- 5.14 Design Example - Reaction Timer -- 5.14.1 Register Transfer Level (RTL) Code -- 5.15 Timing Analysis of Flip-flop Circuits -- 5.15.1 Timing Analysis with Clock Skew -- 5.16 Concluding Remarks -- 5.17 Examples of Solved Problems -- Problems -- Chapter 6: Synchronous Sequential Circuits -- 6.1 Basic Design Steps -- 6.1.1 State Diagram -- 6.1.2 State Table -- 6.1.3 State Assignment -- 6.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions -- 6.1.5 Timing Diagram -- 6.1.6 Summary of Design Steps -- 6.2 State-Assignment Problem -- 6.2.1 One-Hot Encoding -- 6.3 Mealy State Model -- 6.4 Design of Finite State Machines Using CAD Tools -- 6.4.1 VHDL Code for Moore-Type FSMs -- 6.4.2 Synthesis of VHDL Code. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 6.4.3 Simulating and Testing the Circuit -- 6.4.4 An Alternative Style of VHDL Code -- 6.4.5 Summary of Design Steps When Using CAD Tools -- 6.4.6 Specifying the State Assignment in VHDL Code -- 6.4.7 Specification of Mealy FSMs Using VHDL -- 6.5 Serial Adder Example -- 6.5.1 Mealy-Type FSM for Serial Adder -- 6.5.2 Moore-Type FSM for Serial Adder -- 6.5.3 VHDL Code for the Serial Adder -- 6.6 State Minimization -- 6.6.1 Partitioning Minimization Procedure -- 6.6.2 Incompletely Specified FSMs -- 6.7 Design of a Counter Using the Sequential Circuit Approach -- 6.7.1 State Diagram and State Table for a Modulo-8 Counter -- 6.7.2 State Assignment -- 6.7.3 Implementation Using D-Type Flip-Flops -- 6.7.4 Implementation Using JK-Type Flip-Flops -- 6.7.5 Example-A Different Counter -- 6.8 FSM as an Arbiter Circuit -- 6.9 Analysis of Synchronous Sequential Circuits -- 6.10 Algorithmic State Machine (ASM) Charts -- 6.11 Formal Model for Sequential Circuits -- 6.12 Concluding Remarks -- 6.13 Examples of Solved Problems -- Problems -- Chapter 7: Digital System Design -- 7.1 Bus Structure -- 7.1.1 Using Tri-State Drivers to Implement a Bus -- 7.1.2 Using Multiplexers to Implement a Bus -- 7.1.3 VHDL Code for Specification of Bus Structures -- 7.2 Simple Processor -- 7.3 A Bit-Counting Circuit -- 7.4 Shift-and-Add Multiplier -- 7.5 Divider -- 7.6 Arithmetic Mean -- 7.7 Sort Operation -- 7.8 Clock Synchronization and Timing Issues -- 7.8.1 Clock Distribution -- 7.8.2 Flip-Flop Timing Parameters -- 7.8.3 Asynchronous Inputs to Flip-Flops -- 7.8.4 Switch Debouncing -- 7.9 Concluding Remarks -- Problems -- Chapter 8: Optimized Implementation of Logic Functions -- 8.1 Multilevel Synthesis -- 8.1.1 Factoring -- 8.1.2 Functional Decomposition -- 8.1.3 Multilevel NAND and NOR Circuits -- 8.2 Analysis of Multilevel Circuits. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 8.3 Alternative Representations of Logic Functions -- 8.3.1 Cubical Representation -- 8.3.2 Binary Decision Diagrams -- 8.4 Optimization Techniques Based on Cubical Representation -- 8.4.1 A Tabular Method for Minimization -- 8.4.2 A Cubical Technique for Minimization -- 8.4.3 Practical Considerations -- 8.5 Concluding Remarks -- 8.6 Examples of Solved Problems -- Problems -- Chapter 9: Asynchronous Sequential Circuits -- 9.1 Asynchronous Behavior -- 9.2 Analysis of Asynchronous Circuits -- 9.3 Synthesis of Asynchronous Circuits -- 9.4 State Reduction -- 9.5 State Assignment -- 9.5.1 Transition Diagram -- 9.5.2 Exploiting Unspecified Next-State Entries -- 9.5.3 State Assignment Using Additional State Variables -- 9.5.4 One-Hot State Assignment -- 9.6 Hazards -- 9.6.1 Static Hazards -- 9.6.2 Dynamic Hazards -- 9.6.3 Significance of Hazards -- 9.7 A Complete Design Example -- 9.7.1 The Vending-Machine Controller -- 9.8 Concluding Remarks -- 9.9 Examples of Solved Problems -- Problems -- Chapter 10: Computer Aided design Tools -- 10.1 Synthesis -- 10.1.1 Netlist Generation -- 10.1.2 Gate Optimization -- 10.1.3 Technology Mapping -- 10.2 Physical Design -- 10.2.1 Placement -- 10.2.2 Routing -- 10.2.3 Timing Analysis -- 10.3 Concluding Remarks -- References -- Chapter 11: Testing of Logic Circuits -- 11.1 Fault Model -- 11.1.1 Stuck-at Model -- 11.1.2 Single and Multiple Faults -- 11.1.3 CMOS Circuits -- 11.2 Complexity of a Test Set -- 11.3 Path Sensitizing -- 11.3.1 Detection of a Specific Fault -- 11.4 Circuits with Tree Structure -- 11.5 Random Tests -- 11.6 Testing of Sequential Circuits -- 11.6.1 Design for Testability -- 11.7 Built-in Self-Test -- 11.7.1 Built-in Logic Block Observer -- 11.7.2 Signature Analysis -- 11.7.3 Boundary Scan -- 11.8 Printed Circuit Boards -- 11.8.1 Testing of PCBs -- 11.8.2 Instrumentation -- 11.9 Concluding Remarks. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Problems. |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on publisher supplied metadata and other sources. |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2026. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Digitization. |
| 655 #4 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Vranesic, Zvonko. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| Main entry heading | Brown, Stephen |
| Title | Fundamentals of Digital Logic with Vhdl Design |
| Place, publisher, and date of publication | New York : McGraw-Hill US Higher Ed ISE,c2022 |
| International Standard Book Number | 9781260597783 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) | |
| Corporate name or jurisdiction name as entry element | ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://ebookcentral.proquest.com/lib/ppks/detail.action?docID=6843013">https://ebookcentral.proquest.com/lib/ppks/detail.action?docID=6843013</a> |
| Public note | Click to View |
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