Golshan, Khosrow. <br/><br/>
ASIC Design Implementation Process :  A Complete Framework. 

 - 1st ed. 
 - 1 online resource (143 pages) 
<br/><br/>Intro -- Foreword -- Trademarks -- Preface -- Acknowledgments -- Disclaimer -- Contents -- About the Author -- Chapter 1: Design Requirements -- 1.1 Specifications -- 1.2 Architecture -- 1.3 Initial Design -- 1.4 Summary -- References -- Chapter 2: Design Validation -- 2.1 FPGA Design -- 2.2 FPGA Programming -- 2.3 Reference Board Design -- 2.4 Hardware and&#xA0;Software Validation -- 2.5 Summary -- References -- Chapter 3: Design Synthesis -- 3.1 Timing Constraints -- 3.2 Optimization Constraints -- 3.3 Design Rule Constraints -- 3.4 Summary -- References -- Chapter 4: Physical Design -- 4.1 Floorplanning -- 4.2 Placement -- 4.3 Clock Tree Synthesis -- 4.4 Routing -- 4.5 Summary -- References -- Chapter 5: Design Verification -- 5.1 Functional Verification -- 5.2 Timing Verification -- 5.3 Physical Verification -- 5.4 Summary -- References -- Chapter 6: ASIC Testing -- 6.1 Functional Test -- 6.2 Scan Test -- 6.3 Boundary Scan Test -- 6.4 Fault Detection -- 6.5 Parametric Test -- 6.6 Current and&#xA0;Very Low-Level Voltage Test -- 6.7 Built-In-Self-Test -- 6.8 Parallel Module Test -- 6.9 System Test -- 6.10 Summary -- References -- Chapter 7: ASIC Qualification -- 7.1 Electro-Static Discharge Test -- 7.2 Latch-up Test -- 7.3 Wafer Acceptance Test -- 7.4 Summary -- References -- Index. 
<br/><br/><label>ISBN: </label>9783031586538 
<br/><br/><label>Index Terms--Genre/Form: </label><br/>Electronic books.
<br/><br/><label>LC Class. No.: </label>TK7867-7867.5 
<br/><br/><label>Dewey Class. No.: </label>621.3815