Digital design : principles and practices / John F. Wakerly.

Includes bibliographical references and index.

1.1 About Digital Design 1 -- 1.2 Analog versus Digital 3 -- 1.3 Digital Devices 6 -- 1.4 Electronic Aspects of Digital Design 7 -- 1.5 Software Aspects of Digital Design 9 -- 1.6 Integrated Circuits 12 -- 1.7 Programmable Logic Devices 15 -- 1.8 Application-Specific ICs 16 -- 1.9 Printed-Circuit Boards 18 -- 1.10 Digital-Design Levels 18 -- 1.11 Name of the Game 22 -- 1.12 Going Forward 23 -- 2 Number Systems and Codes 25 -- 2.1 Positional Number Systems 26 -- 2.2 Octal and Hexadecimal Numbers 27 -- 2.3 General Positional-Number-System Conversions 29 -- 2.4 Addition and Subtraction of Nondecimal Numbers 32 -- 2.5 Representation of Negative Numbers 34 -- 2.5.1 Signed-Magnitude Representation -- 2.5.2 Complement Number Systems -- 2.5.3 Radix-Complement Representation -- 2.5.4 Two's-Complement Representation -- 2.5.5 Diminished Radix-Complement Representation -- 2.5.6 Ones'-Complement Representation -- 2.5.7 Excess Representations -- 2.6 Two's-Complement Addition and Subtraction 39 -- 2.6.1 Addition Rules -- 2.6.2 A Graphical View -- 2.6.3 Overflow -- 2.6.4 Subtraction Rules -- 2.6.5 Two's-Complement and Unsigned Binary Numbers -- 2.7 Ones'-Complement Addition and Subtraction 44 -- 2.8 Binary Multiplication 45 -- 2.9 Binary Division 47 -- 2.10 Binary Codes for Decimal Numbers 48 -- 2.11 Gray Code 51 -- 2.12 Character Codes 53 -- 2.13 Codes for Actions, Conditions, and States 53 -- 2.14 n-Cubes and Distance 57 -- 2.15 Codes for Detecting and Correcting Errors 58 -- 2.15.1 Error-Detecting Codes -- 2.15.2 Error-Correcting and Multiple-Error-Detecting Codes -- 2.15.3 Hamming Codes -- 2.15.4 CRC Codes -- 2.15.5 Two-Dimensional Codes -- 2.15.6 Checksum Codes -- 2.15.7 m-out-of-n Codes -- 2.16 Codes for Serial Data Transmission and Storage 69 -- 2.16.1 Parallel and Serial Data -- 2.16.2 Serial Line Codes -- 3 Digital Circuits 79 -- 3.1 Logic Signals and Gates 80 -- 3.2 Logic Families 84 -- 3.3 CMOS Logic 86 -- 3.3.1 CMOS Logic Levels -- 3.3.2 MOS Transistors -- 3.3.3 Basic CMOS Inverter Circuit -- 3.3.4 CMOS NAND and NOR Gates -- 3.3.5 Fan-In -- 3.3.6 Noninverting Gates -- 3.3.7 CMOS AND-OR-INVERT and OR-AND-INVERT Gates -- 3.4 Electrical Behavior of CMOS Circuits 96 -- 3.4.2 Data Sheets and Specifications -- 3.5 CMOS Steady-State Electrical Behavior 99 -- 3.5.1 Logic Levels and Noise Margins -- 3.5.2 Circuit Behavior with Resistive Loads -- 3.5.3 Circuit Behavior with Nonideal Inputs -- 3.5.4 Fanout -- 3.5.5 Effects of Loading -- 3.5.6 Unused Inputs -- 3.5.7 Current Spikes and Decoupling Capacitors -- 3.5.8 How to Destroy a CMOS Device -- 3.6 CMOS Dynamic Electrical Behavior 113 -- 3.6.1 Transition Time -- 3.6.2 Propagation Delay -- 3.6.3 Power Consumption -- 3.7 Other CMOS Input and Output Structures 123 -- 3.7.1 Transmission Gates -- 3.7.2 Schmitt-Trigger Inputs -- 3.7.3 Three-State Outputs -- 3.7.4 Open-Drain Outputs -- 3.7.5 Driving LEDs -- 3.7.6 Multisource Buses -- 3.7.7 Wired Logic -- 3.7.8 Pull-Up Resistors -- 3.8 CMOS Logic Families 135 -- 3.8.1 HC and HCT -- 3.8.2 VHC and VHCT -- 3.8.3 HC, HCT, VHC, and VHCT Electrical Characteristics -- 3.8.4 FCT and FCT-T -- 3.8.5 FCT-T Electrical Characteristics -- 3.9 Bipolar Logic 145 -- 3.9.1 Diodes -- 3.9.2 Diode Logic -- 3.9.3 Bipolar Junction Transistors -- 3.9.4 Transistor Logic Inverter -- 3.9.5 Schottky Transistors -- 3.10 Transistor-Transistor Logic 156 -- 3.10.1 Basic TTL NAND Gate -- 3.10.2 Logic Levels and Noise Margins -- 3.10.3 Fanout -- 3.10.4 Unused Inputs -- 3.10.5 Additional TTL Gate Types -- 3.11 TTL Families 166 -- 3.11.1 Early TTL Families -- 3.11.2 Schottky TTL Families -- 3.11.3 Characteristics of TTL Families -- 3.11.4 A TTL Data Sheet -- 3.12 CMOS/TTL Interfacing 170 -- 3.13 Low-Voltage CMOS Logic and Interfacing 171 -- 3.13.1 3.3-V LVTTL and LVCMOS Logic -- 3.13.2 5-V Tolerant Inputs -- 3.13.3 5-V Tolerant Outputs -- 3.13.4 TTL/LVTTL Interfacing Summary -- 3.13.5 2.5-V and 1.8-V Logic -- 3.14 Emitter-Coupled Logic 175 -- 3.14.1 Basic CML Circuit -- 3.14.2 ECL 10K/10H Families -- 3.14.3 ECL 100K Family -- 3.14.4 Positive ECL (PECL) -- 4 Combinational Logic Design Principles 193 -- 4.1 Switching Algebra 194 -- 4.1.1 Axioms -- 4.1.2 Single-Variable Theorems -- 4.1.3 Two- and Three-Variable Theorems -- 4.1.4 n-Variable Theorems -- 4.1.5 Duality -- 4.1.6 Standard Representations of Logic Functions -- 4.2 Combinational-Circuit Analysis 209 -- 4.3 Combinational-Circuit Synthesis 215 -- 4.3.1 Circuit Descriptions and Designs -- 4.3.2 Circuit Manipulations -- 4.3.3 Combinational-Circuit Minimization -- 4.3.4 Karnaugh Maps -- 4.3.5 Minimizing Sums of Products -- 4.3.6 Simplifying Products of Sums -- 4.3.7 "Don't-Care" Input Combinations -

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