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| 001 | EBC6579168 | ||
| 003 | MiAaPQ | ||
| 005 | 20250821091803.0 | ||
| 006 | m o d | | ||
| 007 | cr cnu|||||||| | ||
| 008 | 250807s2021 xx o ||||0 eng d | ||
| 020 |
_a9783030644482 _q(electronic bk.) |
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| 020 | _z9783030644475 | ||
| 035 | _a(MiAaPQ)EBC6579168 | ||
| 035 | _a(Au-PeEL)EBL6579168 | ||
| 035 | _a(OCoLC)1250090416 | ||
| 040 |
_aMiAaPQ _beng _erda _epn _cMiAaPQ _dMiAaPQ |
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| 100 | 1 | _aTehranipoor, Mark. | |
| 245 | 1 | 0 | _aEmerging Topics in Hardware Security. |
| 250 | _a1st ed. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing AG, _c2021. |
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| 264 | 4 | _c�2021. | |
| 300 | _a1 online resource (614 pages) | ||
| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 505 | 0 | _aIntro -- Preface -- Contents -- Contributors -- Acronyms -- 1 Blockchain-Enabled Electronics Supply Chain Assurance -- 1.1 Introduction -- 1.2 Preliminaries -- 1.2.1 Counterfeit Mitigation Techniques -- 1.2.1.1 Counterfeit Detection -- 1.2.1.2 Counterfeit Avoidance and Design for Anti-Counterfeit -- 1.2.2 Blockchain and Decentralized Ledgers -- 1.3 Blockchain-Enabled Electronics Supply Chain -- 1.3.1 Participants in Electronics Supply Chain -- 1.3.2 Integrity Concerns in Electronics Supply Chain -- 1.3.3 Additional Challenges in Electronics Supply Chain -- 1.3.4 Notation and Terminology -- 1.3.5 Assumptions -- 1.4 Framework for the Blockchain-Enabled Electronics SupplyChain -- 1.4.1 Consortium Ledger: The Certificate Authentication Network -- 1.4.2 Blockchain-Enabled Electronics Supply Chain Framework -- 1.4.2.1 Enrollment -- 1.4.2.2 Ownership Release -- 1.4.2.3 Verification -- 1.4.2.4 Ownership Acquire -- 1.4.3 IP Owner and Foundry (OCM) -- 1.4.4 Assembly Stage -- 1.4.4.1 PCB Assembly -- 1.4.4.2 System Integration -- 1.4.5 End User -- 1.4.6 Distribution Stage -- 1.4.7 Electronic Waste -- 1.5 Evaluation of the Method -- 1.5.1 Resistance Against Recycling -- 1.5.2 Resistance Against Overproduction -- 1.5.3 Resistance Against Remarking -- 1.5.4 Resistance Against Cloning -- 1.6 Conclusion -- References -- 2 Digital Twin with a Perspective from Manufacturing Industry -- 2.1 Introduction -- 2.2 Digital Twin -- 2.2.1 Evolution of Digital Twin -- 2.2.2 Definitions of DT from Different Perspectives -- 2.2.2.1 Digital Twin vs. Digital Thread -- 2.2.2.2 Definition of DT with Different Key Points -- 2.3 What a Working DT Would Look Like? -- 2.3.1 Three-Dimensional Framework -- 2.3.2 Five-Dimensional Framework -- 2.4 DT-driven Product Design -- 2.4.1 Conceptual Design -- 2.4.2 Detailed Design -- 2.4.3 Virtual Verification. | |
| 505 | 8 | _a2.5 Security Issues in Digital Twin -- 2.6 Semiconductor Manufacturing -- 2.6.1 Overview of Semiconductor Manufacturing -- 2.6.2 Core Part of Semiconductor Manufacturing: Wafer Fabrication -- 2.7 DT for Semiconductor Manufacturing (Wafer Fabrication): Perspective of Job Scheduling -- 2.7.1 Need for Efficient Job Scheduling During Wafer Fabrication -- 2.7.2 Taxonomy of Job Scheduling Problem -- 2.7.2.1 Batch Processing Problem -- 2.7.2.2 Scheduling Under Constraint of Auxiliary Resources -- 2.7.2.3 Multiple Orders per Job Scheduling Problem -- 2.7.3 Solution Techniques for Job Scheduling Problems -- 2.7.3.1 Batching Problem -- 2.7.3.2 Scheduling Under Constraint of Auxiliary Resources -- 2.7.3.3 Multiple Orders per Job Scheduling Problem -- 2.7.4 Why Do We Employ DT for EfficientJob Scheduling? -- 2.8 Building a Mature DT System in Semiconductor Fields: Challenges and Research Opportunities -- 2.8.1 Semiconductor Production Digitalization for Design -- 2.8.1.1 What Are the Current Methods for Manufacturing Digitalization? -- 2.8.2 Semiconductor Manufacturing Modeling Strategies -- 2.8.2.1 A Possible Way? -- 2.8.2.2 What Are the Current Methods for Manufacturing Modeling Strategies? -- 2.8.3 Production Optimization: Improving the Manufacturing Efficiency -- 2.8.3.1 Traditional Statistical Process Control (SPC) and Advanced Process Control -- 2.8.3.2 Problems for Semiconductor Manufacturing -- 2.8.3.3 What Are the Current Methods for DT Based Production Optimization? -- 2.8.4 Identifying Useful Data -- 2.8.5 Summarizing Disparate Source of Data -- 2.8.6 Bring More External Data -- 2.8.7 Privacy and Security -- 2.9 Conclusion -- References -- 3 Trillion Sensors Security -- 3.1 Introduction -- 3.2 Taxonomy of Sensors -- 3.2.1 Applications -- 3.2.2 Operating Principles -- 3.2.3 Technology -- 3.3 Infrastructure for Sensor-Based Applications. | |
| 505 | 8 | _a3.4 Security Analysis -- 3.4.1 Device Identity Verification -- 3.4.1.1 Attack Vectors -- 3.4.1.2 Countermeasures -- 3.4.2 Secure Communication -- 3.4.2.1 Traditional Approaches -- 3.4.2.2 Low-Cost Approaches -- 3.4.3 Secure Storage -- 3.4.4 Access Control -- 3.5 Conclusion -- References -- 4 Security of AI Hardware Systems -- 4.1 Artificial Intelligence System -- 4.1.1 An Example of Neural Network System -- 4.1.2 Hardware in AI Systems -- 4.2 Security Threats and Countermeasures -- 4.2.1 Data Poisoning -- 4.2.2 Evasion Attack -- 4.2.3 Inversion Attack -- 4.3 System Level Hardware Solutions for AI Systems -- 4.3.1 Trusted Execution Environments -- 4.3.2 IoT-AI Accelerator-Server -- 4.3.3 Summary -- References -- 5 Machine Learning in Hardware Security -- 5.1 IP Protection -- 5.1.1 Security Issues in Hardware IP andCountermeasures -- 5.1.2 Hardware Obfuscation -- 5.1.3 Logic Locking -- 5.1.4 Possible Attacks on Logic Locking and Countermeasures -- 5.1.4.1 Conventional Functional Attacks -- 5.1.4.2 Countermeasures Against the SAT-Attack -- 5.1.4.3 Threats from Machine Learning (ML) -- 5.1.5 ML-Based Functional Attack on SAT-Resistant Logic Locking -- 5.1.6 ML-Based Structural Attack on SAT-Resistant Logic Locking -- 5.1.7 Future Work Against ML-Based Attacks -- 5.2 ML-Assisted HW Trojan Detection -- 5.2.1 Preliminaries of Hardware Trojan -- 5.2.2 Overview of the Hardware Trojan Detection Based on Machine Learning (ML) Algorithms -- 5.2.3 Case Study of ML-Assisted Hardware TrojanDetection -- 5.2.3.1 ML-Assisted Logic Test -- 5.2.3.2 ML-Assisted Side-Channel Analysis -- 5.2.3.3 ML-Assisted Cross-Sectional Photography -- 5.2.4 Summary -- 5.3 ML-Assisted Side-Channel Analysis -- 5.3.1 Profiled SCA -- 5.3.2 Feature Selection in SCA -- 5.3.2.1 Principal Component Analysis (PCA) -- 5.3.2.2 Kullback-Leibler (KL) Divergence -- 5.3.2.3 Other Approaches. | |
| 505 | 8 | _a5.3.3 Classification for SCA -- 5.3.3.1 Support Vector Machine (SVM) -- 5.3.3.2 Random Forest and Rotation Forest -- 5.3.3.3 Other Approaches -- 5.3.4 SCA Against Machine Learning Models -- 5.3.5 Hierarchical Attack and Solution to ImbalancedClasses -- 5.4 ML-Based Attacks Against HW Security Primitives -- 5.4.1 PUF Overview -- 5.4.1.1 Arbiter-Based PUF -- 5.4.1.2 Ring Oscillator PUF -- 5.4.2 Machine Learning Attacks on PUFs -- 5.4.2.1 Machine Learning Methods -- 5.4.2.2 Attacks on Standard PUFs -- 5.4.2.3 Attacks on Feed-Forward PUFs -- 5.4.2.4 Walk into Reality -- 5.4.2.5 Cooperation with Side Channels -- 5.4.3 Another Hardware Primitive -- 5.4.4 Summary -- 5.5 Hardware-Related System/Architecture Security -- 5.5.1 System Security: Malware Detection -- 5.5.1.1 Malware and Its Classification -- 5.5.1.2 Overview of Hardware-Assisted Malware Detection with Machine Learning -- 5.5.1.3 Commonly Used Machine-Learning Methods in HMD -- 5.5.1.4 Case Study of ML-Based Hardware-Assisted Malware Detection -- 5.6 Future of ML-Involved Hardware Security -- References -- 6 Security Assessment of High-Level Synthesis -- 6.1 Introduction -- 6.2 Conventional ASIC Design Flow -- 6.2.1 Defining Specification -- 6.2.2 Architecture Selection -- 6.2.3 RTL Design and Verification -- 6.2.4 Physical Design -- 6.2.5 Tape-Out -- 6.3 HLS Based Design Flow -- 6.3.1 HLS Steps -- 6.4 What Is Obfuscation and Why Is It Necessary? -- 6.5 Secure High-Level Synthesis for Hardware Obfuscation -- 6.6 HLS Security -- 6.6.1 HLS Optimizations -- 6.6.2 Potential Security Vulnerabilities Due to HLS Optimizations -- 6.6.3 Case Studies -- 6.6.3.1 Unbalanced Pipeline Depths -- 6.6.3.2 Generation of Combinational Circuits -- 6.6.3.3 Uncleared Intermediate and I/O Registers -- 6.6.4 Automated Verification and Prevention Strategies -- 6.7 Need for Secure HLS for Obfuscation -- 6.8 Summary. | |
| 505 | 8 | _aReferences -- 7 CAD for Side-Channel Leakage Assessment -- 7.1 Introduction -- 7.2 Preliminaries: Power Side-Channel Attacks -- 7.3 Side-Channel Leakage Assessment -- 7.3.1 Post-Silicon Leakage Assessment -- 7.3.2 Simulation Based Leakage Assessment -- 7.3.3 Pre-silicon Leakage Assessment -- 7.3.4 Pre- vs. Post-Silicon Leakage Assessment -- 7.4 SCRIPT Framework for Pre-silicon Leakage Assessment -- 7.4.1 Threat Model -- 7.4.2 Properties of Target Function -- 7.4.3 Identifying Target Registers Using IFT -- 7.4.3.1 IFT Engine -- 7.4.3.2 Target Registers Identification -- 7.4.3.3 Target Registers of AES -- 7.4.4 SCV Metric -- 7.4.4.1 SPG (SCV-Guided Pattern Generation) -- 7.4.4.2 SPG for AES -- 7.4.4.3 Noise Power Estimation -- 7.4.5 Experimental Results: SCRIPT -- 7.4.5.1 AES Benchmarks -- 7.4.5.2 Results: SCV Estimation and Validation -- 7.5 RTL-PSC: Side-Channel Leakage Vulnerability Evaluation Framework -- 7.5.1 RTL-PSC Workflow -- 7.5.2 Evaluation Metrics -- 7.5.3 Selection of a Key Pair -- 7.5.4 Identification of Vulnerable Designs and Blocks -- 7.5.5 Experiment Results: RTL-PSC -- 7.6 Conclusion -- References -- 8 Post-Quantum Hardware Security -- 8.1 Introduction -- 8.2 Quantum Computing and Cryptography: A Brief Overview -- 8.3 Quantum Computing for Side-Channel Analysis -- 8.3.1 SCA in Classic World -- 8.3.2 SCA in Quantum World -- 8.3.2.1 Post-Quantum Cryptographic Algorithms -- 8.3.2.2 SCA on Code-Based Post-Quantum Cryptographic Schemes -- 8.3.2.3 SCA by Quantum Computer on Classical Algorithms -- 8.4 Random Number Generators -- 8.4.1 Attacks Against TRNGs and QRNGs -- 8.4.1.1 Attacks Against QRNGs -- 8.5 Physically Unclonable Functions -- 8.5.1 PUF Preliminaries: Pre-quantum Era -- 8.5.2 Defense: Innovative PUF Architectures for Anti-Counterfeiting and for Preventing Quantum Attacks -- 8.5.2.1 Classical Quantum-Secure PUFs. | |
| 505 | 8 | _a8.5.2.2 Quantum-Secure Authentication of PUFs. | |
| 588 | _aDescription based on publisher supplied metadata and other sources. | ||
| 590 | _aElectronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2025. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. | ||
| 655 | 4 | _aElectronic books. | |
| 776 | 0 | 8 |
_iPrint version: _aTehranipoor, Mark _tEmerging Topics in Hardware Security _dCham : Springer International Publishing AG,c2021 _z9783030644475 |
| 797 | 2 | _aProQuest (Firm) | |
| 856 | 4 | 0 |
_uhttps://ebookcentral-proquest-com.mlisicats.remotexs.co/lib/ppks/detail.action?docID=6579168&query=9783030644482 _zClick to View |
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