000			02857nam a22004093i 4500
001			EBC31471650
003			MiAaPQ
005			20250825095851.0
006			m o d |
007			cr cnu||||||||
008			250807s2024 xx o ||||0 eng d
020			_a9783031586538 _q(electronic bk.)
020			_z9783031586521
035			_a(MiAaPQ)EBC31471650
035			_a(Au-PeEL)EBL31471650
035			_a(OCoLC)1439601709
040			_aMiAaPQ _beng _erda _epn _cMiAaPQ _dMiAaPQ
050		4	_aTK7867-7867.5
082	0		_a621.3815
100	1		_aGolshan, Khosrow.
245	1	0	_aASIC Design Implementation Process : _bA Complete Framework.
250			_a1st ed.
264		1	_aCham : _bSpringer, _c2024.
264		4	_c�2024.
300			_a1 online resource (143 pages)
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
505	0		_aIntro -- Foreword -- Trademarks -- Preface -- Acknowledgments -- Disclaimer -- Contents -- About the Author -- Chapter 1: Design Requirements -- 1.1 Specifications -- 1.2 Architecture -- 1.3 Initial Design -- 1.4 Summary -- References -- Chapter 2: Design Validation -- 2.1 FPGA Design -- 2.2 FPGA Programming -- 2.3 Reference Board Design -- 2.4 Hardware and Software Validation -- 2.5 Summary -- References -- Chapter 3: Design Synthesis -- 3.1 Timing Constraints -- 3.2 Optimization Constraints -- 3.3 Design Rule Constraints -- 3.4 Summary -- References -- Chapter 4: Physical Design -- 4.1 Floorplanning -- 4.2 Placement -- 4.3 Clock Tree Synthesis -- 4.4 Routing -- 4.5 Summary -- References -- Chapter 5: Design Verification -- 5.1 Functional Verification -- 5.2 Timing Verification -- 5.3 Physical Verification -- 5.4 Summary -- References -- Chapter 6: ASIC Testing -- 6.1 Functional Test -- 6.2 Scan Test -- 6.3 Boundary Scan Test -- 6.4 Fault Detection -- 6.5 Parametric Test -- 6.6 Current and Very Low-Level Voltage Test -- 6.7 Built-In-Self-Test -- 6.8 Parallel Module Test -- 6.9 System Test -- 6.10 Summary -- References -- Chapter 7: ASIC Qualification -- 7.1 Electro-Static Discharge Test -- 7.2 Latch-up Test -- 7.3 Wafer Acceptance Test -- 7.4 Summary -- References -- Index.
588			_aDescription based on publisher supplied metadata and other sources.
590			_aElectronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2025. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
655		4	_aElectronic books.
776	0	8	_iPrint version: _aGolshan, Khosrow _tASIC Design Implementation Process _dCham : Springer,c2024 _z9783031586521
797	2		_aProQuest (Firm)
856	4	0	_uhttps://ebookcentral-proquest-com.mlisicats.remotexs.co/lib/ppks/detail.action?docID=31471650&query=9783031586538 _zClick to View
942			_2lcc _cEB
999			_c1964 _d1964