Practical Digital Design : (Record no. 1948)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 06446nam a22004093i 4500 |
| 001 - CONTROL NUMBER | |
| control field | EBC6795402 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20250821093103.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 250807s2022 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781612497679 |
| Qualifying information | (electronic bk.) |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (MiAaPQ)EBC6795402 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (Au-PeEL)EBL6795402 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)1315643039 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | MiAaPQ |
| Language of cataloging | eng |
| Description conventions | rda |
| -- | pn |
| Transcribing agency | MiAaPQ |
| Modifying agency | MiAaPQ |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Reidenbach, Bruce. |
| 245 10 - TITLE STATEMENT | |
| Title | Practical Digital Design : |
| Remainder of title | An Introduction to VHDL. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | West Lafayette, IN : |
| Name of producer, publisher, distributor, manufacturer | Purdue University Press, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2022. |
| 264 #4 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Date of production, publication, distribution, manufacture, or copyright notice | �2022. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (445 pages) |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Cover -- PRACTICAL DIGITAL DESIGN -- Title -- Copyright -- Dedication -- TABLE OF CONTENTS -- PREFACE -- ACKNOWLEDGMENTS -- ABOUT THE AUTHOR -- CHAPTER 1 INTRODUCTION -- Target Audience -- A Brief History of Digital Design -- The Need for a Hardware Description Language -- A Brief Tour of a VHDL Model -- CHAPTER 2 SIGNALS, TIME, AND THE SIMULATION CYCLE -- Signals -- Events -- Drivers -- Delta Time -- The Simulation Cycle -- CHAPTER 3 THE VHDL DESIGN ENVIRONMENT -- Modeling Styles -- Design Flow -- Data Types -- Type Definition -- Vector Data Types -- Operators and Precedence -- Design Libraries -- Predefined Packages -- STANDARD Package -- STD_LOGIC_1164 Package -- NUMERIC_STD Package -- TEXTIO Package -- Type Conversion -- Type Qualification -- Attributes -- VHDL Language Versions -- Coding Style -- Vertical Alignment -- VHDL Identifier Naming Rules -- Comments -- CHAPTER 4 DECLARATIONS -- Syntax Notation -- Object Declaration Syntax -- Custom Type Declarations -- Integer Types -- Floating Point Types -- Enumerated Types -- Array Types -- Record Types -- Physical Types -- Access Types -- Alias Declarations -- CHAPTER 5 LIBRARIES AND DESIGN UNITS -- Library Units -- Entity Declaration -- Ports -- Generics -- Architecture Declaration -- Package Declaration -- Package Body Declaration -- Configuration Declaration -- Design Units -- Context Clause -- Summary -- CHAPTER 6 CONCURRENT STATEMENTS -- Conditional Signal Assignment Statement -- Selected Signal Assignment Statement -- Waveform Specification -- Delay Models -- Generate Statement -- Component Instantiation -- Concurrent Assertion Statement -- Component Declaration -- Configuration Specification -- Component Instantiation Statement -- Direct Entity Instantiation -- Block Statement -- Process Statement -- Summary -- CHAPTER 7 SEQUENTIAL STATEMENTS -- Null Statement -- Wait Statement. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | If Statement -- Case Statement -- Loop Statement -- Loop Control Statements -- Assertion and Report Statements -- Signal Assignment -- Variable Assignment -- Summary -- CHAPTER 8 THE PROCESS STATEMENT -- Process Review -- Combinatorial Logic -- Level Sensitive Latches -- Clocked Logic -- Process Examples -- Register Files -- Shift Registers -- Adders -- Counters -- State Machines -- Memory Arrays -- Process Construction Guidelines -- Summary -- CHAPTER 9 MODELING CASE STUDIES -- Modeling Style -- Binary Adder -- Behavioral Model -- Synthesizable Model -- Structural Model -- Summary -- Engine Management System -- CHAPTER 10 SUBPROGRAMS -- Functions -- Return Statements -- Examples -- Overloading -- Pure versus Impure Functions -- Procedures -- Return Statements -- Parameter Passing Details -- Signal Parameters -- Concurrent Procedure Calls -- Procedures as Functions -- Summary -- CHAPTER 11 SIMULATION AND TEST BENCHES -- Simulation -- Simulation Phases -- Test Benches -- Test Bench Control -- Races -- Input Drivers -- Output Monitors -- Test Bench Example -- Test Bench Types -- Directed Testing -- Constrained Random Testing -- Golden Vectors -- Combination Test Benches -- Summary -- CHAPTER 12 TEST BENCH DEVELOPMENT -- Test Bench Templates -- Regression Testing -- Test Suites -- Code Coverage -- Summary -- CHAPTER 13 TEST BENCH CASE STUDIES -- Clocked Full Adder -- Engine Management System -- Summary -- CHAPTER 14 LOGIC SYNTHESIS -- Synthesis Phases -- Synthesis Steps -- Synthesis -- Implementation -- Implementation Checks -- Device Programming -- Quartus Prime Synthesis Steps -- Summary -- CHAPTER 15 ASIC AND FPGA TECHNOLOGY -- Digital Logic Technology -- CMOS Technology -- ASIC Implementation -- Gate Arrays -- FPGAs -- Summary -- CHAPTER 16 SYNTHESIS CODE EXAMPLES -- Concurrent Logic -- Data Multiplexers -- Register Files -- Shift Registers. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Adders -- Addition -- Subtraction -- Overflow Protection -- Addition/Subtraction -- Counters -- Clock Dividers -- Loop Unrolling -- Tri-State I/O Drivers -- A More Complex Example -- Summary -- CHAPTER 17 SPECIALIZED CODE EXAMPLES -- FPGA Resources -- Multipliers -- Multiply/Accumulate -- RAM Blocks -- Distributed RAM -- Block RAM -- ROM Blocks -- RAM Design Examples -- RAM-Based Shift Register -- RAM-Based FIFO Buffer -- Summary -- CHAPTER 18 STATE MACHINES -- State Machine Basics -- State Machine Design -- Inputs and Outputs -- Design Example -- Summary -- CHAPTER 19 FUNCTIONAL DECOMPOSITION -- The Functional Decomposition Process -- Examples -- Summary -- CHAPTER 20 FILTER DESIGN EXAMPLE -- Background -- Functional Decomposition -- Logic Design -- Test Bench Development -- Logic Synthesis -- Architecture Improvement -- Summary -- CHAPTER 21 DESIGN REUSE -- Generics -- Test Benches -- Data Handshaking -- Design Example -- Summary -- APPENDIX A CODING STYLE GUIDELINES -- APPENDIX B FUNCTIONAL DESCRIPTION EXAMPLE -- SPI Interface -- APPENDIX C VHDL RESERVED WORDS -- STATEMENT INDEX -- SUBJECT INDEX. |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on publisher supplied metadata and other sources. |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2025. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | VHDL (Computer hardware description language). |
| 655 #4 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| Main entry heading | Reidenbach, Bruce |
| Title | Practical Digital Design |
| Place, publisher, and date of publication | West Lafayette, IN : Purdue University Press,c2022 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) | |
| Corporate name or jurisdiction name as entry element | ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://ebookcentral-proquest-com.mlisicats.remotexs.co/lib/ppks/detail.action?docID=6795402&query=9781612497679">https://ebookcentral-proquest-com.mlisicats.remotexs.co/lib/ppks/detail.action?docID=6795402&query=9781612497679</a> |
| Public note | Click to View |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Library of Congress Classification |
| Koha item type | E-Book |
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