Practical Digital Design : An Introduction to VHDL.

Cover -- PRACTICAL DIGITAL DESIGN -- Title -- Copyright -- Dedication -- TABLE OF CONTENTS -- PREFACE -- ACKNOWLEDGMENTS -- ABOUT THE AUTHOR -- CHAPTER 1 INTRODUCTION -- Target Audience -- A Brief History of Digital Design -- The Need for a Hardware Description Language -- A Brief Tour of a VHDL Model -- CHAPTER 2 SIGNALS, TIME, AND THE SIMULATION CYCLE -- Signals -- Events -- Drivers -- Delta Time -- The Simulation Cycle -- CHAPTER 3 THE VHDL DESIGN ENVIRONMENT -- Modeling Styles -- Design Flow -- Data Types -- Type Definition -- Vector Data Types -- Operators and Precedence -- Design Libraries -- Predefined Packages -- STANDARD Package -- STD_LOGIC_1164 Package -- NUMERIC_STD Package -- TEXTIO Package -- Type Conversion -- Type Qualification -- Attributes -- VHDL Language Versions -- Coding Style -- Vertical Alignment -- VHDL Identifier Naming Rules -- Comments -- CHAPTER 4 DECLARATIONS -- Syntax Notation -- Object Declaration Syntax -- Custom Type Declarations -- Integer Types -- Floating Point Types -- Enumerated Types -- Array Types -- Record Types -- Physical Types -- Access Types -- Alias Declarations -- CHAPTER 5 LIBRARIES AND DESIGN UNITS -- Library Units -- Entity Declaration -- Ports -- Generics -- Architecture Declaration -- Package Declaration -- Package Body Declaration -- Configuration Declaration -- Design Units -- Context Clause -- Summary -- CHAPTER 6 CONCURRENT STATEMENTS -- Conditional Signal Assignment Statement -- Selected Signal Assignment Statement -- Waveform Specification -- Delay Models -- Generate Statement -- Component Instantiation -- Concurrent Assertion Statement -- Component Declaration -- Configuration Specification -- Component Instantiation Statement -- Direct Entity Instantiation -- Block Statement -- Process Statement -- Summary -- CHAPTER 7 SEQUENTIAL STATEMENTS -- Null Statement -- Wait Statement.

If Statement -- Case Statement -- Loop Statement -- Loop Control Statements -- Assertion and Report Statements -- Signal Assignment -- Variable Assignment -- Summary -- CHAPTER 8 THE PROCESS STATEMENT -- Process Review -- Combinatorial Logic -- Level Sensitive Latches -- Clocked Logic -- Process Examples -- Register Files -- Shift Registers -- Adders -- Counters -- State Machines -- Memory Arrays -- Process Construction Guidelines -- Summary -- CHAPTER 9 MODELING CASE STUDIES -- Modeling Style -- Binary Adder -- Behavioral Model -- Synthesizable Model -- Structural Model -- Summary -- Engine Management System -- CHAPTER 10 SUBPROGRAMS -- Functions -- Return Statements -- Examples -- Overloading -- Pure versus Impure Functions -- Procedures -- Return Statements -- Parameter Passing Details -- Signal Parameters -- Concurrent Procedure Calls -- Procedures as Functions -- Summary -- CHAPTER 11 SIMULATION AND TEST BENCHES -- Simulation -- Simulation Phases -- Test Benches -- Test Bench Control -- Races -- Input Drivers -- Output Monitors -- Test Bench Example -- Test Bench Types -- Directed Testing -- Constrained Random Testing -- Golden Vectors -- Combination Test Benches -- Summary -- CHAPTER 12 TEST BENCH DEVELOPMENT -- Test Bench Templates -- Regression Testing -- Test Suites -- Code Coverage -- Summary -- CHAPTER 13 TEST BENCH CASE STUDIES -- Clocked Full Adder -- Engine Management System -- Summary -- CHAPTER 14 LOGIC SYNTHESIS -- Synthesis Phases -- Synthesis Steps -- Synthesis -- Implementation -- Implementation Checks -- Device Programming -- Quartus Prime Synthesis Steps -- Summary -- CHAPTER 15 ASIC AND FPGA TECHNOLOGY -- Digital Logic Technology -- CMOS Technology -- ASIC Implementation -- Gate Arrays -- FPGAs -- Summary -- CHAPTER 16 SYNTHESIS CODE EXAMPLES -- Concurrent Logic -- Data Multiplexers -- Register Files -- Shift Registers.

Adders -- Addition -- Subtraction -- Overflow Protection -- Addition/Subtraction -- Counters -- Clock Dividers -- Loop Unrolling -- Tri-State I/O Drivers -- A More Complex Example -- Summary -- CHAPTER 17 SPECIALIZED CODE EXAMPLES -- FPGA Resources -- Multipliers -- Multiply/Accumulate -- RAM Blocks -- Distributed RAM -- Block RAM -- ROM Blocks -- RAM Design Examples -- RAM-Based Shift Register -- RAM-Based FIFO Buffer -- Summary -- CHAPTER 18 STATE MACHINES -- State Machine Basics -- State Machine Design -- Inputs and Outputs -- Design Example -- Summary -- CHAPTER 19 FUNCTIONAL DECOMPOSITION -- The Functional Decomposition Process -- Examples -- Summary -- CHAPTER 20 FILTER DESIGN EXAMPLE -- Background -- Functional Decomposition -- Logic Design -- Test Bench Development -- Logic Synthesis -- Architecture Improvement -- Summary -- CHAPTER 21 DESIGN REUSE -- Generics -- Test Benches -- Data Handshaking -- Design Example -- Summary -- APPENDIX A CODING STYLE GUIDELINES -- APPENDIX B FUNCTIONAL DESCRIPTION EXAMPLE -- SPI Interface -- APPENDIX C VHDL RESERVED WORDS -- STATEMENT INDEX -- SUBJECT INDEX.

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Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2025. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.